Tetra Replication

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verpies

Re: Tetra Replication « Reply #200 on: 2025-03-08, 20:22:02 »

Group: Professor
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Posts: 3666

Quote from: bte on 2025-03-08, 14:57:18

Need to get timing board sent out for fabrication...

Does that mean that you have its schematic?
If "yes", can we see it?

bte

Re: Tetra Replication « Reply #201 on: 2025-03-08, 23:29:10 »

Group: Moderator
Sr. Member

Posts: 308

Quote from: verpies on 2025-03-08, 20:22:02

Does that mean that you have its schematic?
If "yes", can we see it?

Sure, here is the timing board schematic. I haven't finished the board so if there is something you see that could be better please let me know.

I opted to use a NOR gate approach to reset the flip flops to avoid the ring counter getting out of sync. With the NOR gate, it auto-corrects itself should it get out of sync, and ensures a 1 propagates properly. Since the NOR gate slightly delays one of the phases I opted to feed the other two out of the same NOR gate chip (via the Q/ output on different circuits within the NOR gate package) to equalize the delay to all phases.

The driver chip is capable of driving multiple 50 ohm lines at 5V, so I opted to pair them up to lower chip count and ensure uniform pulses for each phase to the A coil driver. There are going to be 3 separate A coil drivers, which will connect to coil A in parallel.

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Tetra Replication

timing-schematic.png (53.25 kB, 1215x707 - viewed 198 times.)

verpies	Re: Tetra Replication « Reply #202 on: 2025-03-09, 00:06:44 »
Group: Professor Hero Member Posts: 3666	It's a mistake not to use the finest step size timing chip DS1023S-25 for NMR purposes.

bte	Re: Tetra Replication « Reply #203 on: 2025-03-09, 00:16:34 »
Group: Moderator Sr. Member Posts: 308	Quote from: verpies on 2025-02-26, 18:03:54 When you apply a high frequency HV pulse to such coils, high electric current flows through these capacitances - not in the copper wire ! At high frequencies these capacitances dominate and the coil behaves more like a capacitor than a coil. This begs a question - why bother with a coil at all ? Why not build a good capacitor instead ? Found this that might offer more insight. Not enough known to speculate what exactly is going on yet - if I can get some positive results and document the parameters, maybe a better picture will unfold. I believe he did try using plates (as per a capacitor) rather than coils but didn't get a good result. Attached in more pertinent comments and a link to the extra correspondences. ------------------------ missed-chats (2).pdf (164.04 kB - downloaded 10 times.) Tetra Replication more-info.png (19.54 kB, 717x172 - viewed 195 times.)

verpies	Re: Tetra Replication « Reply #204 on: 2025-03-09, 00:43:10 »
Group: Professor Hero Member Posts: 3666	Quote from: bte on 2025-03-08, 23:29:10 I opted to use a NOR gate approach to reset the flip flops to avoid the ring counter getting out of sync. You are not using the NOR gate to reset the flip-flops in case of an error. You are using it for state decoding. That approach can create glitches if the states of the flip-flops do not change at the same time. That is very different than using NOR gates to reset the flip-flops via their asynchronous CLR or PReset inputs. Error correction implemented with gates and the asynchronous flip-flop inputs would look like this: IMO error correction is superfluous. « Last Edit: 2025-03-09, 14:11:49 by verpies »

bte	Re: Tetra Replication « Reply #205 on: 2025-03-09, 02:14:22 »
Group: Moderator Sr. Member Posts: 308	Are you sure that the d flip flops will preset and reset at the right time to garuntee proper operation?

verpies	Re: Tetra Replication « Reply #206 on: 2025-03-09, 21:25:21 »
Group: Professor Hero Member Posts: 3666	Quote from: bte on 2025-03-09, 02:14:22 Are you sure that the d flip flops will preset and reset at the right time to garuntee proper operation? Yes Also, despite them being logically equivalent, one method of connecting unused inputs of NOR gates is faster because, in a CMOS circuit, charging two gate input capacitances is slower than one. Also, didn't you want to generate the clock on-board with additional DS1023 chips ?

bte	Re: Tetra Replication « Reply #207 on: 2025-03-09, 21:46:01 »
Group: Moderator Sr. Member Posts: 308	Quote from: verpies on 2025-03-09, 21:25:21 Yes Also, despite them being logically equivalent, one method of connecting unused inputs of NOR gates is faster because, in a CMOS circuit, charging two gate input capacitances is slower than one. Also, didn't you want to generate the clock on-board with additional DS1023 chips ? Okay, I reverted to your set/preset version. I think this should work, does it look okay? The DS1023 has identical pinouts for the different range versions of the chip, so disregard the 50ns version used here. Edit: hopefully the labels makes the schematic easier to read. ------------------------ Tetra Replication timing-schematic2.png (58.76 kB, 1245x729 - viewed 154 times.)

verpies	Re: Tetra Replication « Reply #208 on: 2025-03-09, 23:23:13 »
Group: Professor Hero Member Posts: 3666	Why do you think that the DS1023 chips cannot drive the MOSFET drivers directly and you need the THS3111 as buffers ?

bte	Re: Tetra Replication « Reply #209 on: 2025-03-09, 23:29:54 »
Group: Moderator Sr. Member Posts: 308	Quote from: verpies on 2025-03-09, 23:23:13 Why do you think that the DS1023 chips cannot drive the MOSFET drivers directly and you need the THS3111 as buffers ? They'll be driving 50 ohm coax into the driver boards. I'm setting it up so that all of the lines are terminated properly so at high speed it doesn't cause any glitches. The point of separating the boards is so I can tune the coax lengths to account for any delay mismatches in the driver boards. Also to experiment with delayed signals in the future if need be. Trying to make it modular.

verpies	Re: Tetra Replication « Reply #210 on: 2025-03-09, 23:46:00 »
Group: Professor Hero Member Posts: 3666	Which end of the coax cable do you plan to terminate with 50Ω ?

bte	Re: Tetra Replication « Reply #211 on: 2025-03-09, 23:50:54 »
Group: Moderator Sr. Member Posts: 308	driver side

verpies	Re: Tetra Replication « Reply #212 on: 2025-03-10, 19:47:37 »
Group: Professor Hero Member Posts: 3666	You might find the attached chapter about Intercard Connections informative: ------------------------ Intercard connections.pdf (662.25 kB - downloaded 23 times.)

verpies	Re: Tetra Replication « Reply #213 on: 2025-03-17, 06:25:51 »
Group: Professor Hero Member Posts: 3666	Look at the rise and fall times as well as pulse widths, that this guy is able to achieve with modern SiC MOSFETs and freewheeling flyback diode. https://youtu.be/Od8XmFk3Tm0