PM
thanks for this revised schematic, it now clearly shows that the "input" is being measured "behind" the MOSFET driver stage.
So the input / output measurement is only done for that part behind the driver stage.
This makes it hard to create a feedback loop as the "input" is pulsed DC (square wave 50% duty cycle) and the output is DC.
If we include the FG and MOSFET driver stage then the input would be 100 times higher, see my post #259. Perhaps we can reduce that significantly by using Peterae's mentioned circuit in his post #261. I am waiting for the correct parts to try that.
Itsu
I'm a little confused by your post Itsu, and I'm not 100% clear on PM's revised schematic. What I see on the schematic, is an input voltage measurement (CH1, YEL), and in the previous schematic there was a current probe on the input. It appears the revised schematic is now using a CVR (CH4 voltage) at the output end of the circuit to provide the input current measurement, is this correct PM? (CH2-CH4 also provides for the voltage across Rload for Pout). Pin is computed via CH1 x CH4? btw PM, does the sim show COP>1? Also, is the Pin result the same in the sim regardless if i(in) is taken at L1 or R1?
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