OTOH, if the synchronous fets are on and conducting current from the secondary to the load for most of the cycle and then turned off for a short period, the secondary current and mmf rapidly reverses.
I agree. That reversal happens during one half of high frequency LC oscillation and is vividly described by GG in his MIT video around the time index 1h05m (with water in an aquarium analogy) During this time, the fet drains are subjected to a high voltage pulse which is generated by the collapse of the secondary current.
I agree The current reversal is created by the discharge of the energy stored in the fet's drain to gate and drain to source capacitances created by the peak voltage and current.
Not only in capacitance but also in the inductance of the transformer. Capacitances do not react to an open circuit with high voltage - inductances do. If the fet should avalanche at too low a voltage, the current reversal will be less than desired for proper operation. This action would then justify the high voltage fets used in G's circuit IMO.
I agree P.S. Did you ever try to model 4 isolated DC voltage sources being switched by ideal switches into the gates of these MOSFETs forming the "synchronous diode" and calculating how much current from these 4 sources gets to the "output terminals" of this "synchronous diode" ?
« Last Edit: 2016-08-19, 16:30:15 by verpies »
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