This looks to me that a glitch is causing (via what? induction / capacitance) a pulse on the gate which triggers the MOSFET again etc. etc.
Via the Drain-Gate capacitance (a.k.a. Miller's capacitance). The purpose of that recent Miller testing setup was to test how much that high dv/dt waveform appearing on the drain, influences the gate voltage when that test gate is terminated by THE SAME impedance as the driving impedance of the other MOSFET gate. Varying the gate driving impedance by several Ohms will exacerbate or minimize the effect of the Drain-Gate capacitance during high dv/dt Drain waveforms. So this proposition can be empirically verified in that manner. ANOTHER ISSUE: From your scopeshot it is evident that there is a double, negative going, pulse when there is a large delay between the two channels. According to the Lenz law the half of the bifilar winding, that is being driven, should induce a pulse of an OPPOSITE polarity in the other half of bifilar winding, that is NOT being driven. ...but this is not what is being observed. Fortunately the mutual capacitance of these two halves of winding can be used to explain two pulses of the same polarity, ...meaning that in this coil the capacitve coupling is stronger than the inductive coupling. In fact the entire bifilar coil can be characterized by the ratio of the capacitive coupling to the inductive coupling ...or treated as a distributed capacitance and inductance, which can be analyzed as a transmission line.
« Last Edit: 2018-11-17, 23:27:00 by verpies »
|