Aye, GroundLoop's circuit (a group of or'd OR gates) as a consequence of critically inserted inverters is a sound solution. Peterae's observation: It is well known that NOTed gates cannot be cascaded
is so very true. And I therefore am eating Crow for making a hasty (and therefore wasteful) mental determination. Truth Tables should always be done with paper and pencil to avoid errors, particularly in advanced years when minds are more like leaky buckets (ie. my bucket has a hole in it.) This discussion has become quite the learning experience! What are the rules for handling unused inputs and outputs? (in general)
With CMOS logic it is most important to disable unused gates on a chip to eliminate the possibility of noise pickup by "floating inputs" which can affect the entire chip. TTL logic chips aren't quite as vulnerable so in many applications unused gates can be left "floating" without troubles. Unused gates can always be paralleled with used same gates to assure that all gates are connected.
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