Drift Step Recovery Diodes seem to be the best way today to produce high power pulses (up to GW) at ns time rise, and with simple means. I have put some papers about the subject here:
http://exvacuo.free.fr/div/Sciences/Dossiers/Electronique/Pulse/
The current waveform applied to the DSR diode can be generated by many different techniques, such as: a pulse transformer with saturable core, inductive flyback pulse, dual switch scheme, etc.
The DSR diode pulse generator depicted in Fig. 8 consists of two circuits with a fast power transistor Q1 (e.g.: MOSFET or IGBT, GaAs BJT, etc...) between them.
The first circuit is composed of inductive energy storage L1 and the second circuit is composed of a capacitive storage C2, inductive storage L2 and DSR Diode D1 (connected in parallel with the load resistor R1). Note that L2, C2, Q1 and D1/R1 form a series RLC circuit. Hereafter this circuit will be referred to as simply: the series RLC circuit.
The capacitor C1 is used to stabilize the supply voltage and decrease the effective internal resistance of the power supply at high frequencies.
Before the impulse generation begins, the transistor Q1 is not conducting (the circuit is open between the drain and source terminals) and the capacitor C2 is charged up to the power supply voltage via the load resistor R1.
To begin nanopulse generation, a short pulse is applied to the gate of Q1 causing it to start conducting.
As soon as the transistor Q1 starts conducting, two events take place:
1) The capacitor C2 discharges through the forward conduction of D1 and
2) the inductances L2 & L1 start accumulating energy (the currents through them increase).
The current through L2 is inherently periodic if the series LCR circuit, formed by L2, C2, Q1RDS-ON and D1/R1, is underdamped, that is: its total resistance is less than 2(L/C)0.5. The period of this oscillation is equal to 1/( 1/LC - R2/4L2 )0.5.
After approximately one-half of this oscillation period (after interval T1), the transistor Q1 stops conducting. See Fig.2.
During the interval T1 the D1 diode was conducting forward and charge was injected into its P-N junction.
For the manifestation of the DSR effect it is very important that the T1 interval is short enough (in the hundreds of ns) to not allow the injected charge to reach the other side of the P-N junction.
During the T1 interval, the periodic current through the series LCR circuit has reached its peak and and decreased back to zero. At the beginning of the interval T2 the current through D1 begins to reverse its direction due to the transient oscillation of the series RLC circuit, effectively causing D1 to conduct in reverse and gradually deplete the charge injected into its P-N junction during T1.
From the beginning of interval T2 the current flowing through L1 joins with current flowing through L2, D1, C1, C2 and R1. As soon as the charge injected into the P-N junction of D1 decreases to zero, the DSR diode abruptly stops conducting. This happens at the end of interval T2.
Because this abrupt interruption happens when non-zero reverse (negative) current flows through D1, L1, L2, C1, C2 and R1, a high voltage pulse appears across the D1 terminals due to the self-induction effect.
The rise time of this pulse is determined by inductance L1 and L2 and the reverse capacitance of D1.
The energy accumulated in L1 from the beginning of Q1' conduction and in L2 during the D1's reverse conduction (T2) is converted into a high electric potential appearing on the D1's reverse capacitance.
The peak power of this pulse is approximately equal to the product of the interrupted current magnitude, determined by the impedances the associated components, and the reverse capacitance of the DSR diode D1.
In order to maximize the DSR diode effect, the forward current through the diode should be lower and of longer duration, yet the reverse current should be higher and of shorter duration.
If forward and reverse current waveforms are the same then the DSR diode stops conducting when the current through the diode is equal to zero and the DSR effect disappears.
An optimal operating point for the DSR effect occurs when the DSR diode stops conducting at the peak of its reverse current.
P.S.
L1 and L2 should be air core inductors wound with a thick wire and positioned perpendicularly and away from each other.
The capacitors should be designed for RF pulse operation. The leads of all components should be soldered as short as possible.
I am attaching a rough
English translation of a Russian document, that describes the DSR Diodes and the operation of the saturable transformer driver that started this thread.
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Topic: DSRD pulse generator (Read 200795 times)
